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MRF89XA
3.4.13
DATA OUTPUT
3.5
Control Block Description
After OOK or FSK demodulation, the baseband signal
is made available to the user on the DATA pin (pin 20),
3.5.1
SPI INTERFACE
when Continuous mode is selected. In Buffered and
Packet modes, the data is retrieved from the FIFO
through the SPI.
During Receive mode, the received data is filled into
the Shift register and then transferred onto the FIFO
stack. The FIFO is configured to generate an interrupt
For more information on standard SPI between the
MRF89XA and a Microcontroller, refer to Section 2.11,
Serial Peripheral Interface (SPI) .
3.5.2 SPI REGISTERS
The registers associated with SPI communication are:
after receiving a defined number of bits.
When the internal FIFO is enabled, the FIFO interrupt,
which is configured through the IRQ0 and IRQ1 pins
(pin 21 and 22), acts as a FIFOFULL interrupt,
indicating that the FIFO has been filled to its
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GCONREG ( Register 2-1 )
DMODREG ( Register 2-2 )
FDEVREG ( Register 2-3 )
BRSREG ( Register 2-4 )
preprogrammed limit. The receiver starts filling the
FIFO with data when it identifies the synchronous
3.6
FIFO Handling
pattern through the synchronous pattern recognition
circuit. It is recommended to set the threshold to at
least half the length of the register (8 bits) to ensure that
the external host microcontroller has time to set up.
The synchronous pattern recognition circuit prevents
the FIFO from being filled up with noise, and therefore
avoids overloading the external host microcontroller.
The hardware description of the FIFO is described in
Section 2.12, FIFO and Shift Register (SR) . The FIFO
is handled by selecting the size of the FIFO, FIFO inter-
rupts, and clearing the FIFO.
3.6.1 SIZE SELECTION
The FIFO width is programmable to 16, 32, 48 or 64
3.4.14
RECEIVE MODE REGISTERS
bytes using the FSIZE<1:0> bits (FIFOCREG<7:6>).
The registers associated with Receive mode are:
3.6.2
INTERRUPT SOURCES AND FLAGS
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GCONREG ( Register 2-1 )
DMODREG ( Register 2-2 )
FDEVREG ( Register 2-3 )
BRSREG ( Register 2-4 )
FLTHREG ( Register 2-5)
FIFOCREG ( Register 2-6 )
FTXRXIREG ( Register 2-14 )
FTPRIREG ( Register 2-14 )
RSTHIREG ( Register 2-16 )
FILCREG ( Register 2-17 )
PFCREG ( Register 2-18 )
SYNCREG ( Register 2-19 )
RSTSREG ( Register 2-21 )
OOKCREG ( Register 2-22 )
SYNCV31REG ( Register 2-23 )
SYNCV23REG ( Register 2-24 )
SYNCV15REG ( Register 2-25 )
SYNCV07REG ( Register 2-26 )
The MRF89XA generates an interrupt request for the
host microcontroller by pulling the IRQ0 or IRQ1 pins
low or high based on the events and configuration set-
tings of these interrupts. All interrupt sources and flags
are configured through the Interrupt Configuration reg-
isters, based on the occurrence of the following events:
? Interrupt Requests (IRQ0 and IRQ1) during differ-
ent receive stand-by data modes (such as Contin-
uous, Buffer and Packet) for following event
occurrences: SYNC, RSSI, PLREADY, ARDS-
MATCH and /FIFOEMPTY.
For example, Write Byte. The WRITEBYTE inter-
rupt source goes high for one bit period each time
a new byte is transferred from the shift register to
the FIFO (that is, each time a new byte is
received).
? Interrupt Requests (IRQ0 and IRQ1) during trans-
mit modes (such as Continuous, Buffer and
Packet) for the following event occurrences: Data
Clock, FIFOFULL, Transmit Done, Transmit Start
with IRQ0 and IRQ1.
For example, TX Done. The TXDONE interrupt
source goes high when the FIFO is empty and the
Shift register ’s last bit has been sent to the modu-
lator (that is, the last bit of the packet has been
sent). One bit period delay is required after the ris-
ing edge of TXDONE to ensure correct RF trans-
mission of the last bit. In practice this may not
require special care in the MCU software due to
IRQ processing time.
DS70622C-page 70
Preliminary
? 2010–2011 Microchip Technology Inc.
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